Core Fusion - Reconfigurable Chip Multiprocessor Architecture

TitleCore Fusion - Reconfigurable Chip Multiprocessor Architecture
OwnerCornell University


Cornell researchers have developed a novel, reconfigurable Chip Multiprocessor (CMP) architecture where groups of adjacent cores can be dynamically fused into larger, more powerful processors based on software demand. This architecture provides a single execution model across all configurations, requires no additional programming or specific compiler support, and leverages mature microarchitecture technology and existing instruction set architectures. Reconfiguration can take place both prior to execution and at run-time.

The unique chip architecture is organized on a standard substrate, with an array of small, identical cores that can function independently, or fused together in groups of two or four. To manage action and communication between the dynamic core formations, a fetch management unit (FMU), and steering management unit (SMU) were created. An application can request fusion or splitting actions through FUSE and SPLIT ISA instructions.



  • Significantly improved performance
    • Dynamically adapts to changing workload demands
    • Increased speed of sequential programs or sequential regions in parallel programs
  • Requires no instruction set architectures (ISA) changes or significant compiler support
  • Reduced manufacturing costs by:
    • Allowing for smoother transitions through software evolution
    • Utilizing a single design for all applications
Applicants:Cornell University
Access to additional documentation:Please inquire
Application number:please inquire
Inventors:betaAbout WellspringAbout Flintbox Innovation Sphere͐
Support from inventors:Please inquire
Publication date:2012-07-20
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